Limits Management Hardware - DCVS

The LMH-DCVS block is a hardware IP for every CPU cluster, to handle quick
changes in thermal limits. The hardware responds to thermal variation amongst
the CPUs in the cluster by requesting limits on the clock frequency and
voltage on the OSM hardware.

The LMH DCVS driver exports a virtual sensor that can be used to set the
thermal limits on the hardware. LMH DCVS driver can be a platform CPU Cooling
device, which registers with the CPU cooling device interface. All CPU device
nodes should reference the corresponding LMH DCVS hardware in device tree.
CPUs referencing the same LMH DCVS node will be associated with the
corresponding cooling device as related CPUs.

Properties:

- compatible:
	Usage: required
	Value type: <string>
	Definition: shall be "qcom,msm-hw-limits"
- interrupts:
	Usage: required
	Value type: <interrupt_type interrupt_number interrupt_trigger_type>
	Definition: Should specify interrupt information about the debug
			interrupt generated by the LMH DCVSh hardware. LMH
			DCVSh hardware will generate this interrupt whenever
			it makes a new cpu DCVS decision.
- qcom,affinity:
	Usage: Required
	Value type: <u32>
	Definition: Should specify the cluster affinity this hardware
			corresponds to.

- isens_vref_1p8-supply:
- isens_vref_0p8-supply:
	Usage: optional
	Value type: <phandle>
	Definition: Should specify the phandle of the vref regulator used by
			the isens hardware. This active only regulator will be
			enabled by LMH DCVSh. Isens hardware needs 1.8v and
			0.8v supply regulators.

- isens-vref-1p8-settings:
- isens-vref-0p8-settings:
	Usage: optional
	Value type: <u32 array>
	Definition: Should specify the min voltage(uV), max voltage(uV) and
			max load(uA) for the isens vref regulator. This
			property is valid only if there is valid entry for
			isens_vref_1p8-supply and isens_vref_0p8-supply.

- reg:
	Usage: Required
	Value type: <a b>
	Definition: where 'a' is the starting register address of the OSM/LLM
			and 'b' is the size of OSM/LLM address space. The
			register space in index 0 should be LLM and index 1
			should be OSM.

- qcom,plat-mitigation-disable:
	Usage: optional
	Value type: <none>
	Definition: Should define this property if platform based cpu cooling
			device is not required.

Example:

	lmh_dcvs0: qcom,limits-dcvs@18350800 {
		compatible = "qcom,msm-hw-limits";
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		qcom,affinity = <0>;
		isens_vref_1p8-supply = <&pm8998_l1_ao>;
		isens-vref-1p8-settings = <880000 880000 36000>;
		isens_vref_0p8-supply = <&pm8998_l12_ao>;
		isens-vref-0p8-settings = <880000 880000 36000>;
		reg =  <0x18350800 0x1000>, //LLM
			<0x18323000 0x1000>; //OSM
		qcom,plat-mitigation-disable;
	};

	CPU0: cpu@0 {
		device_type = "cpu";
		compatible = "arm,armv8";
		reg = <0x0 0x0>;
		qcom,lmh-dcvs = <&lmh_dcvs0>;;
	};