Qualcomm Technologies, Inc. QCS405 CPU clock driver
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It is the clock controller driver which provides higher frequency
clocks and allows CPU frequency scaling on qcs405 based platforms.

Required properties:
- compatible:	Shall contain following:
		"qcom,cpu-qcs405"
		"qcom,cpu-sdxprairie"
- clocks:	Phandle to the clock device.
- clock-names:	Names of the used clocks. Shall contain following:
		"xo_ao", "gpll0_ao"
- reg:	Shall contain base register offset and size.
- reg-names:	Names of the bases for the above registers. Shall contain following:
		"apcs_cmd", "apcs_pll"
- vdd_dig_ao-supply:	The regulator(active only) powering the digital logic of APSS PLL.
- vdd_hf_pll-supply:	The regulator(active only) powering the Analog logic of APSS PLL.
- cpu-vdd-supply:	The regulator powering the APSS RCG.
- qcom,speedX-bin-vZ:	A table of CPU frequency (Hz) to regulator voltage (uV) mapping.
			Format: <freq uV>
			This represents the max frequency possible for each possible
			power configuration for a CPU that's binned as speed bin X,
			speed bin revision Z. Version can be between [0-3].
- #clock-cells:	Shall contain 1.

Optional properties:
- reg-names:	"efuse"
- qcom,cpucc-init-rate:	Initial rate which needs to be set from cpu driver.

Example:
	clock_cpu: qcom,clock-cpu@0b011050 {
		compatible = "qcom,cpu-qcs405";
		clocks = <&clock_rpmcc RPM_SMD_XO_A_CLK_SRC>,
			<&clock_gcc GPLL0_AO_OUT_MAIN>;
		clock-names = "xo_ao", "gpll0_ao" ;
		qcom,cpucc-init-rate = <960000000>;
		reg = <0x0b011050 0x8>,
			<0xb016000 0x34>;
		reg-names = "apcs_cmd" , "apcs_pll";
		cpu-vdd-supply = <&apc_vreg_corner>;
		vdd_dig_ao-supply = <&pmd9655_s1_level_ao>;
		vdd_hf_pll-supply = <&pms405_l5_ao>;
		qcom,speed0-bin-v0 =
			< 0         0>,
			< 960000000  1>,
			< 1113600000 2>,
			< 1267200000 3>,
			< 1382400000 4>;
		#clock-cells = <1>;
	};

	clock_cpu: qcom,clock-cpu@17808100 {
		compatible = "qcom,cpu-sdxprairie";
		clocks = <&clock_rpmh RPMH_CXO_CLK>>;
		clock-names = "&clock_rpmh RPMH_CXO_CLK";
		reg = <0x17810008 0x8>,
			<0x17808100 0x44>;
		reg-names = "apcs_cmd" , "apcs_pll";
		vdd-lucid-pll-supply = <&VDD_CX_LEVEL_AO>;
		cpu-vdd-supply = <&VDD_CX_LEVEL_AO>;
		qcom,speed0-bin-v0 =
			<          0 RPMH_REGULATOR_LEVEL_OFF>,
			<  345600000 RPMH_REGULATOR_LEVEL_LOW_SVS>,
			<  576000000 RPMH_REGULATOR_LEVEL_SVS>,
			< 1094400000 RPMH_REGULATOR_LEVEL_NOM>,
			< 1555200000 RPMH_REGULATOR_LEVEL_TURBO>;
		#clock-cells = <1>;
	};