Qualcomm Technologies, Inc. Display Clock & Reset Controller Binding
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Required properties :
- compatible : Shall contain one of the following:
		"qcom,dispcc-sm8150",
		"qcom,dispcc-sm8150-v2",
		"qcom,dispcc-sm6150",
		"qcom,dispcc-sdmmagpie",
		"qcom,dispcc-trinket",
		"qcom,dispcc-sdmshrike-v2",
		"qcom,dispcc-sa6155",
		"qcom,atoll-dispcc".
- reg : Shall contain base register location and length.
- reg-names: Address name. Must be "cc_base".
- vdd_mm-supply: phandle to the MM_CX rail that needs to be voted on behalf
		 of the clocks.
- clock-names: Shall contain "cfg_ahb_clk"
- clocks: phandle + clock reference to the GCC AHB clock.
- #clock-cells : Shall contain 1.
- #reset-cells : Shall contain 1.

Example:
	clock_dispcc: qcom,dispcc {
		compatible = "qcom,dispcc-sm8150";
		reg = <0xaf00000 0x20000>;
		reg-names = "cc_base";
		vdd_mm-supply = <&pm8150l_s5_level>;
		clock-names = "cfg_ahb_clk";
		clocks = <&clock_gcc GCC_DISP_AHB_CLK>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};